The present invention relates to digital delay circuits, and more particularly to an electronic delay control circuit that delays an input pulse without changing the pulse width.
In many applications it is desirable to have various pulse signals, such as multiple clock signals, occur at specific time intervals with respect to each other. Careful circuit design can bring the relative timing to within a specified tolerance, but variations in components result in the need to provide some variable delay so that the relative timing can be achieved precisely when the circuit is completed to compensate for such variations. In digital circuits delay may be achieved by inputting a pulse signal to a shift register having a plurality of taps, and then selecting the appropriate tap for the desired delay. The delay is an integer multiple of the clock signal that clocks the shift register, and does not provide for adjustment within the range of values less than one clock cycle. Likewise analog type delay lines with variable components can be used to provide a constantly variable delay time, but such circuits tend to alter the pulse width of the resulting delayed pulse signal. Another technique is to convert the pulse signal into a ramp signal that is input to a comparator for comparison with a variable reference voltage. Again this provides a constantly variable delay time, but at the expense of altering the pulse width of the pulse signal.
What is desired is an electronic delay control circuit that provides a constantly variable delay while maintaining a desired pulse width, i.e., that delays both the leading and trailing edge of the input pulse signal equally.